Device and method for generating a variable duty cycle clock

Abstract

A device for generating a variable duty cycle clock is provided, which includes a frequency divider, a plurality of first M-stage delay elements, a plurality of second M-stage delay elements, a selector and a logic gate, where M is an integer. The frequency divider divides an input clock to obtain a divided clock. The first M-stage delay elements, which are connected in series, sequentially delay the divided clock for a first delay time to obtain M first delay clocks. The second M-stage delay elements, which are also connected in series and are corresponding to the first M-stage delay elements, sequentially delay the divided clock for a second delay time to obtain M second delay clocks. The second delay time is in a variable proportion to the first delay time. The selector compares the divided clock and each of the M first delay clocks to obtain M state signals. The M state signals are used to select a first selected clock corresponding to a period of the input clock from the first delay clocks, and a second selected clock corresponding to the first selected clock from the second delay clocks. The logic gate XORs the divided clock and the second selected clock to obtain the variable duty cycle clock.