The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 21, 2000

Filed:

Sep. 15, 1999
Applicant:
Inventors:

Masayoshi Kinoshita, Osaka, JP;

Shiro Sakiyama, Osaka, JP;

Jun Kajiwara, Kyoto, JP;

Katsuji Satomi, Osaka, JP;

Hiroo Yamamoto, Osaka, JP;

Katsuhiro Ootani, Nara, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G05F / ;
U.S. Cl.
CPC ...
323280 ; 323274 ; 323908 ;
Abstract

A power circuit including means for preventing the generation of an inrush current during the power circuit's initial operation without increasing the size of the power circuit is described. The power circuit comprises an output transistor for supplying a current from a power supply to an output terminal, and a differential amplifier for controlling the current supplied by the output transistor in such a manner as to regulate a voltage at the output terminal based on a preset reference voltage. A limiting transistor is provided as a source follower on a current path at the output stage of the differential amplifier. The gate potential of the output transistor is controlled using the source potential of the limiting transistor. Before the power circuit starts to operate, an operation controller charges a capacitor to control the gate potential of the limiting transistor so that during the initial operation of the power circuit, the capacitor is discharged by using a current source. Accordingly, during the initial operation of the power circuit, the gate potential of the limiting transistor gradually decreases while the gate-source voltage of the output transistor gradually increases. As a result, the generation of the inrush current can be suppressed.


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