The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 21, 2000
Filed:
Sep. 18, 1998
William M Andreycak, Bedford, NH (US);
Robert Monroe, Ashland, MA (US);
Chuck Payne, Cary, NC (US);
Larry Wofford, Cary, NC (US);
Texas Instruments Incorporated, Dallas, TX (US);
Abstract
An electronic device includes a conductive member disposed within an insulative package. The conductive member is formed from a lead frame used to form the interconnection pins for the device. The conductive member includes an elongated, folded sense element portion having a known resistance. The sense element portion is disposed between two sets of conductive lead portions extending from the conductive member forming pins used to provide a current to the device for sensing. An integrated circuit disposed within the package includes a differential amplifier having differential inputs connected to bond pads on the integrated circuit. The bond pads are connected to spaced-apart tap points of the sense element via conductive bond wires, so that the combination of the sense element and the differential amplifier forms a trans-impedance amplifier. The gain of the differential amplifier is controlled to be proportional to the magnitude of a reference voltage generated by a bandgap voltage reference circuit. The reference voltage varies with temperature such that the overall gain of the trans-impedance amplifier is constant over temperature. The nominal gain of the differential amplifier is established by an on-chip resistance, which is trimmed using fuse-programmable trim cells that are programmed via operational package pins during a pre-operation trim procedure.