The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 14, 2000

Filed:

Jan. 08, 1999
Applicant:
Inventor:

Shooji Kitazawa, Tokyo, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C / ;
U.S. Cl.
CPC ...
36518902 ; 36518901 ; 365205 ; 365226 ; 36518909 ;
Abstract

A non-volatile semiconductor memory apparatus having a memory matrix of inter-column arrangement type configuration divided into several segments performs a read operation based on a system that causes a current to flow into sense amplifiers from data lines. In this non-volatile semiconductor memory, memory cell transistors configured as memory cells are serially connected to form multiple memory rows. Word lines connect the gates of the transistors constituting the memory cells of each memory row. First column lines and second column lines connect the connection nodes between the memory cell transistors. The word lines and the first and second column lines constitute a memory array. Bit lines are connected to the second column lines, respectively. A bias electric potential supply line is connected to the first column lines via select transistors, respectively. A multiplexer circuit includes select transistors which select two bit lines as a pair from the bit lines, and connect the selected two bit lines to a data bus pair. Sense amplifiers are connected to the data buses, respectively.


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