The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 14, 2000
Filed:
Oct. 20, 1999
Erkki Miettinen, Helsinki, FI;
ABB Industry OY, Helsinki, FI;
Abstract
An inverter has a direct voltage intermediate circuit having a positive (Udc+) and a negative (Udc-) voltage busbar, and an auxiliary voltage source (1) which generates auxiliary voltages (U1, U2, U3) referenced to the positive (Udc+) and the negative (Udc-) voltage busbar of the direct voltage intermediate circuit. The inverter also has for each phase an upper (2) and a lower (3) power semiconductor, connected in series between the positive and the negative voltage busbar. The point between the semiconductors forms the phase output (Uout) of the inverter. An upper (4) and lower (5) gate driver outputs (8,9) are connected to the control electrode (G) of the respective upper (2) and lower (3) power semiconductors which have a positive (6) and a negative (7) auxiliary voltage input and a zero potential point (Com) connected to the output electrode (E) of the power semiconductor to be controlled. A first diode (D1) has its anode connected to the positive auxiliary voltage (U2) and its cathode connected to the positive auxiliary voltage input (6) of the upper gate driver (4). A first capacitor (C1) is connected between the positive auxiliary voltage input (6) of the upper gate driver (4) and the zero potential point (Com). The inverter also has for each phase another diode (D2), its anode being connected to the negative auxiliary voltage input (7) of the upper gate driver and its cathode being connected to the negative auxiliary voltage (U3). Another capacitor (C2) is connected between the negative auxiliary voltage input (7) and the zero potential point.