The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 14, 2000
Filed:
Dec. 19, 1998
Laszlo Huber, Apex, NC (US);
Jindong Zhang, Blacksburg, VA (US);
Milan M Jovanovic, Cary, NC (US);
Fred C Lee, Blacksburg, VA (US);
Delta Electronics, Inc., Taipei, TW;
Virginia Tech. Intellectual Properties, Inc., Blacksburg, VA (US);
Abstract
A single-stage input-current-shaping (S.sup.2 ICS) converter of the present invention integrates a voltage-doubler-rectifier front-end with a DC/DC output stage. Two families of voltage-doubler S.sup.2 ICS converters are disclosed. In one family, a 2-terminal dither source is provided between a boost inductor and a common input terminal of a storage capacitor and the DC/DC output stage. The 2-terminal dither source includes two paths connected in parallel: a first path for charging and a second path for discharging the boost inductor at a high frequency (HF). In the other family, a 3-terminal dither source includes a third terminal coupled to a pulsating node of the DC/DC output stage. In the 3-terminal dither source, the HF charging path of the boost inductor is coupled between the boost inductor and the pulsating node of the DC/DC output stage, while the HF discharging path of the boost inductor is coupled between the boost inductor and the common input terminal of the storage capacitor and the DC/DC output stage. Due to the voltage-doubler-rectifier front-end, reduction of line-current harmonics can be achieved with a higher conversion efficiency, as compared to a corresponding S.sup.2 ICS converter with a conventional full-bridge rectifier. In addition, a converter of the present invention requires storage capacitors of a lower voltage rating and a smaller total capacitance than the conventional S.sup.2 ICS counterpart. The present invention thereby reduces the size and the cost of the power supply.