The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 14, 2000

Filed:

Dec. 23, 1996
Applicant:
Inventors:

Hidekazu Shibasaki, Higashine, JP;

Hiroaki Ueno, Kawasaki, JP;

Assignee:

Fujitsu Limited, Kawasaki, JP;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G11B / ; G11B / ;
U.S. Cl.
CPC ...
360 46 ; 360 67 ;
Abstract

A signal reproducing circuit includes first power supply lines having different potentials, a magneto-resistive effect head having one end thereof coupled to the first power supply line, for reproducing data recorded on a magnetic recording medium in a read operation, and a first constant current source coupled between another end of the magneto-resistive effect head and the second power supply line, for supplying the magneto-resistive effect head with a sense current in the read operaion. Also included are first and second transistors having collectors thereof coupled to the first power supply line, respectively, and responsive to voltage signals obtained from the one end and the other end of the magneto-resistive effect head. Second and third constant current sources are coupled between each emitter of the first and the second transistors and the second power supply line, respectively, for supplying the first and the second transistors with a first predetermined constant current, respectively, in the read operation. Fourth and fifth constant current sources are provided between each emitter of the first and the second transistors, respectively, and the second power supply line for increasing the emiter curents of the first and the second transistors to a second predetermined constant current during a predetermined period in a transition from a write state to a read state.


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