Phase/frequency detector with time-delayed inputs in a charge pump based

Abstract

A phase locked loop (PLL) circuit with time-delayed phase/frequency detector (PFD) input signals and a method for generating high PFD gain in such a circuit is provided. One circuit embodiment includes a first divider, a phase/frequency detector having a plurality of input pairs, a plurality of input signal reference delay elements connected in a series between the first divider and the PFD, a charge pump, a loop filter, a voltage-controlled oscillator (VCO), a second divider, and a plurality of feedback signal delay elements connected in a series. The corresponding method embodiment includes steps for receiving digital input signals with reference frequency and period T in the first divider, dividing the reference frequency by a value R, providing a plurality of time-delayed PFD reference input signals in each period T, dividing the VCO frequency by a value M in the second divider, and providing a plurality of time-delayed PFD feedback input signals in each period T. The delayed reference signal and the delayed feedback signal at each PFD input pair have the same time delay. Another embodiment circuit has a first divider, a plurality of phase/frequency detectors (PFDs), a charge pump, two OR gates, a loop filter, a voltage-controlled oscillator (VCO), and a second divider. The corresponding method embodiment includes the steps for receiving reference frequency signals in the first divider, dividing the reference frequency by a value R, and creating a plurality of time-delayed reference output signals in each period T for PFD reference inputs, or-ing the output signals from the plurality of the PDFs to supply the charge pump, dividing the VCO frequency by a value M in the second divider, creating a plurality of time-delayed feedback output signals in each period T, and supplying each PFD feedback input with one of the plurality of time-delayed feedback output signals.