The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 14, 2000

Filed:

Apr. 13, 1998
Applicant:
Inventors:

Atsushi Hori, Osaka, JP;

Junichi Kato, Osaka, JP;

Shinji Odanaka, Osaka, JP;

Seiki Ogura, Wappingers Falls, NY (US);

Kaori Akamatsu, Osaka, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L / ;
U.S. Cl.
CPC ...
257317 ; 257321 ;
Abstract

The nonvolatile semiconductor memory device of the invention includes: a semiconductor substrate having a surface including a first surface region at a first level, a second surface region at a second level lower than the first level, and a step side region linking the first and second surface regions; a channel region formed in the first surface region of the semiconductor substrate; a source region and a drain region which are formed in the surface of the semiconductor substrate so as to interpose the channel region therebetween; a first insulating film formed on the surface of the semiconductor substrate; a floating gate formed on the first insulating film; and a control gate capacitively coupled to the floating gate via a second insulating film. The first surface region is an upper surface of an epitaxially grown layer formed on the second surface region. The drain region includes: a low-concentration impurity layer formed in the second surface region and having one end extending toward the step side region; and a high-concentration impurity layer connected to the low-concentration impurity layer and formed in a region distant from the channel region. An impurity concentration of the low-concentration impurity layer is lower than that of the high-concentration impurity layer. The floating gate covers the step side region and at least a part of the low-concentration impurity layer via the first insulating film.


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