The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 14, 2000

Filed:

Sep. 30, 1999
Applicant:
Inventor:

Tae-Hun Roh, Cheongju, KR;

Assignee:

Hyundai Microelectronics Co., Ltd., Choongcheongbuk-Do, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L / ;
U.S. Cl.
CPC ...
438197 ; 438585 ; 438301 ;
Abstract

A method for fabricating a metal-oxide-semiconductor field effect transistor (MOSFET) device, includes: a step of dividing a semiconductor substrate into an active region and an isolation region; a step of forming a first insulation layer on the semiconductor substrate; a step of forming a first polycrystal silicon layer on the first insulation layer; a step of forming a first silicide layer on the first polycrystal silicon layer; a step of forming a second insulation layer on the first silicide layer; a step of patterning the second insulation layer; a step of forming a sidewall spacer at the side portions of the second insulation layer pattern; a step of forming a gate by sequentially etching the first silicide layer, the first polycrystal silicon layer and the first insulation layer by using the second insulation layer pattern and the sidewall spacer as a mask; a step for removing the sidewall spacer; a step of forming an oxide film at the side portions of the gate and at the upper portion of the semiconductor substrate; and a step of sequentially performing a process for forming an impurity region operated as a source/drain at the upper portion of the semiconductor substrate which is adjacent to the gate, thereby providing a stable device property and improving a yield.


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