Series reed-solomon decoder synchronized with bit clock signal

Abstract

The present invention relates to a small size decoder reducing power consumption and more particularly to a series reed-Solomon decoder synchronized with a bit clock signal. In a Reed-Solomon decoder according to the present invention, the syndrome calculation part comprises a classification element for classifying the input coding data into an even data and an odd data and for calculating, in series, coefficient of the syndrome polynomial on bit-by-bit basis, being synchronized with a bit clock signal. The error position and estimation polynomial calculation part comprises a classification element for classifying an initial syndrome polynomial, a correction syndrome polynomial, an initial deletion pointer polynomial and an initial deletion pointer polynomial into an even data and an odd data and for an error value polynomial and an error position value polynomial on bit-by-bit basis, being synchronized with a bit clock signal. The error position polynomial root and error value calculation part comprises a substitution element for substituting roots for the error position polynomial and the error value polynomial, being synchronized with a bit clock signal, for accumulating results of the error position polynomial and the error value polynomial and for outputting error values for error correction, being synchronized with a byte clock signal.