Interface for flexible address bandwidth allocation

Abstract

A processor is connected to one or more controlled devices (e.g., ASICS) using an interface that has a plurality of bandwidth distribution devices (i.e., a controller device and one or more adjunct devices) configured in an architecture having two or more levels. Each bandwidth distribution device receives an allocation of address bandwidth from a device in the next higher level and distributes that allocation of address bandwidth to one or more devices in the next lower level, each of which is either another bandwidth distribution device or a controlled device. Each bandwidth distribution device can be configured independently in different configuration modes that determine how its available address bandwidth is distributed to devices in the next lower level. The different configuration modes allow the number of devices in the next lower level to be traded off with the amount of bandwidth available to a particular device in the next lower level. In this way, the interface architecture of the present invention can be used to support a wide variety of applications in which the number of controlled devices varies from application to application and the amount of required address bandwidth varies from controlled device to controlled device within an application.