Phase-locked loop circuit with equalizer and phase locking method

Abstract

A phase-locked loop circuit, which is used in a radio data communication terminal of the type that obtains a transmission line characteristic during a preamble period in a narrow band modulation mode and equalizes received signals, that can correct an influence due to a phase error even in an environment of frequency selective multipath fading. The phase-locked loop circuit includes a phase rotation section, a replica signal generator, a phase difference detector, a division section, an integration circuit, and a vector converter. An equalizer obtains tap coefficients determined by transmission line characteristics and sets them to the equalizer and the replica signal generator. The equalizer starts to demodulate data and sequentially inputs the demodulated data to the replica signal generator to reproduce I and Q signal components input to the equalizer based on the demodulation data and tap coefficients. The phase difference detector determines a phase difference between a reproduced I signal component and an I signal component to be input to the equalizer adjusted in timing and a phase difference between a reproduced Q signal component and a Q signal component to be input to the equalizer adjusted in timing. The division section arbitrarily weights phase differences. The integration circuit integrates weighted phase differences in symbol units. Then the vector converter converts the integrated value into received signal components and inputs the converted value to the phase rotation section, so that phase errors are corrected.