The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 07, 2000
Filed:
Sep. 07, 1999
Jean-Claude Tarbouriech, Ville-la-Grand, FR;
Motorola Inc., Schaumburg, IL (US);
Abstract
The present invention provides a means for clearing or wiping the contents of a RAM array without the need for overly large transistors and without experiencing current spikes by using a progressive row-by-row clearing operation. In reference to FIGS. 4 and 5, progressive row clearing is achieved by the addition of a transistor (72) in series with the row RAMWIPE transistor (e.g. transistor 69) in each row. Transistor 72 is gated by a signal PRS (Previous Row Select). PRS for a given row will be asserted or enabled only when the previous row in the array is also selected or enabled. A given row is only selected for clearing in a wipe operation when both a RAMWIPE signal and a PRS (previous row select) signal are asserted. The next row, therefore, is not cleared until the previous row is cleared.