The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 07, 2000
Filed:
Feb. 27, 1998
Applicant:
Inventor:
Masaru Sanada, Tokyo, JP;
Assignee:
NEC Corporation, Tokyo, JP;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L / ;
U.S. Cl.
CPC ...
257443 ;
Abstract
A semiconductor integrated circuit having a logic verification structure includes a logic circuit formed by CMOS structure on a semiconductor substrate, in which the semiconductor integrated circuit has an impurity region irradiated by a laser beam from a back of the semiconductor substrate, for testing the logic circuit, achieving a simple logic analysis.
Quick Actions:
Sanada, Masaru. (2000). Semiconductor integrated circuit having a logic verifying structure and (U.S. Patent No. 6144084). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/6144084
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