The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 31, 2000
Filed:
Mar. 31, 1998
Jerome Bombal, La Trinite, FR;
Laurent Souef, Mouans Sartoux, FR;
VLSI Technology, Inc., San Jose, CA (US);
Abstract
The present invention, generally speaking, provides an integrated circuit testing technique in which hardware accessibility of selected components is exploited in order to avoid scan insertion overhead but achieve as good or better fault coverage than if scan insertion had been used. The term 'pseudo-scan' is used to refer to the use of read and write instructions to achieve the equivalent effect as scan insertion without the addition of scan flops. Existing ATPG tools may be used without modification by performing scan insertion on a 'dummy' circuit and performing ATPG on the scan-augmented dummy circuit. The resulting ATPG vectors are then modified to perform pseudo scan of selected components of the original circuit.