Coherence mechanism for distributed address cache in a network switch

Abstract

In a network switch with a distributed address cache, events that update a cache segment are serialized and distributed and acted upon by all the cache segments to maintain consistency among the segments. The segments are individually associated with Input/Output Application Specific Integrated Circuits ('I/O ASICs') interconnected via an event sharing bus used for transmission of cache update messages. Messages are ordered by arbitrating for the shared bus and enforcing that an I/O ASIC does not update its local cache segment until a cache update message is broadcast on the event bus. Each I/O ASIC asserts a busy signal while executing a cache update message to prevent an arbiter from granting the event bus to allow transmission of a subsequent update message; thereby synchronizing all update messages and minimizing storage on each I/O ASIC for update messages. A weakly coherent mechanism predicated on the observation that address learning operations and address aging operations are self correcting is employed which permits cache update messages to be flushed when cache line conflicts are detected.