The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 31, 2000
Filed:
Aug. 26, 1999
Abstract
Clock generating circuits include a clock buffer, a delay mirror circuit (DMC), a clock frequency divider circuit and a clock generator circuit. The clock buffer is responsive to an external clock signal EXTCLK and generates a buffered clock signal ICLK in response to the external clock signal EXTCLK. The buffered clock signal ICLK is delayed relative to the external clock signal EXTCLK by a fixed buffer delay time 'dtb'. The delay mirror circuit (DMC) is responsive to the buffered clock signal ICLK and generates a delayed clock signal IDCLK. The delayed clock signal IDCLK is delayed relative to the buffered clock signal ICLK by a fixed delay-mirror time 'dtot'. The clock frequency divider circuit is responsive to the buffered clock signal ICLK and the delayed clock signal IDCLK. The clock frequency divider circuit includes first and second divider devices that generate first and second divided clock signals VDIV1 and VDIV2, respectively. The clock generator circuit is responsive to VDIV1 and VDIV2 and includes a control signal generator, an analog pump signal generator and a driver circuit. Based on this configuration of the above-described circuits, only 2 clock periods are required before the rising edge of the internal clock signal INTCLK is in-sync and in-phase with the external clock signal EXTCLK.