The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 31, 2000
Filed:
Oct. 28, 1999
Justin A McEldowney, Tucson, AZ (US);
Burr-Brown Corporation, Tucson, AZ (US);
Abstract
An offset-compensated amplifier including an input stage (2) having a current source (10), first (11) and second (12) FETs each having a source connected to the current source, first (17) and second (18) input FETs each having a source connected to a drain of the first compensation FET (11), and third (19) and fourth (20) input FETs each having a source connected to a drain of the second compensation FET (12), a drain of each of the first (17) and third (19) input FETs being connected by a first output conductor (21) to a first load (23), and a drain of each of the second (18) and fourth (20) input FETs being connected by a second output conductor (22) to a second load (24), a gate of each of the first (17) and third (19) input FETs being connected to a first input (3A), a gate of each of the second (18) and fourth (20) FETs being connected to a second input (3B). Auto-zeroing circuitry (3) including switching circuitry (32A, 32B) operative to short-circuit the first (3A) and second (3B) inputs to cause the input stage (2) to produce a gained-up offset voltage between the first (21) and second (22) output conductors, switched capacitor circuitry (26A, 26B, 27A, 27B) operative to store the gained-up offset voltage, and compensation circuitry (28) operative to apply compensation signals to the gates of the first (11) and second (12) compensation FETs in response to the stored gained-up offset voltage.