Self-timed pipelined datapath system and asynchronous signal control

Abstract

A self-timed pipelined datapath system reduces its power dissipation by accurately controlling the active and inactive states of the multi-threshold CMOS (MT-CMOS) circuit used as its combinational circuit. The MT-CMOS circuit comprises a logic circuit of low-threshold and a power control circuit formed of high-threshold transistors for controlling the power feeding to the logic circuit. The self-timed pipelined datapath system comprises: a pipelined datapath circuit including a plurality of data processing stages, each having a combinational circuit for processing input data and a register connected to the input side of the combinational circuit; and an asynchronous signal control circuit that controls data transmission to and from each of the registers in the pipelined datapath circuit in response to a request signal. The state change of an active state to an inactive state of the combinational circuit is performed in consideration of the signal propagation time therein, whereby the issue of the request signal with respect to the combinational circuit at the preceding stage is delayed from the time the request signal with respect to the current combinational circuit is issued.