The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 31, 2000

Filed:

Dec. 30, 1998
Applicant:
Inventors:

Chun-Yu Chen, Albuquerque, NM (US);

Gilles Marcel Ferru, Cairon, FR;

Serge Bardy, Caen, FR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L / ; H01L / ; H01L / ; H01L / ;
U.S. Cl.
CPC ...
257574 ; 257575 ; 257576 ; 438342 ; 438370 ;
Abstract

An integrated injection logic device is provided in which each collector of an I2L gate is isolated by a field oxide ('FOX'), or by other suitable isolation such as, for example, an isolation trench. The connection of the base to the collectors, between the base contact region and the bottom of the collectors, is made underneath the field oxide using a buried p type layer (TN3 in the Figures illustrating the invention). Because both silicide and heavy implant p+ implant is present at the base contact point only, the recombination current is reduced. This reduces the current loss when compared to the current loss of the known device. Additionally, current gain is also improved by placing a deep base implant close to the emitter of the upside down NPN transistor in the integrated logic device. The area of the base and the area of the collectors is decoupled, i.e. one can adjust the base to collector areas and the base contact area, independently to control the total base current, thus allowing more freedom in layout optimization of the I2L gate and allowing more freedom in optimizing the gain of the I2L gate.


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