The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 31, 2000
Filed:
May. 20, 1998
Applicant:
Inventors:
Harlan Sur, San Leandro, CA (US);
Subhas Bothra, San Jose, CA (US);
Assignee:
Philips Semiconductors, Inc., Sunnyvale, CA (US);
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L / ;
U.S. Cl.
CPC ...
438294 ; 438210 ; 438238 ; 438328 ; 438330 ; 438361 ; 438382 ; 438430 ; 257508 ;
Abstract
A small-area, high-resistance load device is fabricated in the same area used for the shallow trench isolation region. In an example embodiment, the load device comprises a series resistor coupled to a poly-silicon diode. In one example application, the load device acts as a pull-up device replacing standard PMOS pull-up loads used in connection with static memory cells, thereby increasing the cell density of a static memory array.
Sur, Harlan. (2000). Semiconductor device having load device with trench isolation region and (U.S. Patent No. 6140188). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/6140188
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile