High-performance lru memory capable of supporting multiple ports

Abstract

In a high performance microprocessor adopting a superscalar technique, necessarily using a cache memory, TLB, BTB and etc. and being implemented by 4-way set associative, there is provided an LRU memory capable of performing a pseudo replacement policy and supporting multi-port required for operating various blocks included in the microprocessor. The LRU memory comprises an address decoding block for decoding an INDEX.sub.-- ADDRESS to produce a READ.sub.-- WORD and a WRITE.sub.-- WORD in response to the first phase and a second phase of the CLOCK signal, respectively; an LRU storing block; a way hit decoding block for decoding a WAY.sub.-- HIT to produce a MODIFY CONTROL signal in response to the second phase of the CLOCK signal; a data modifying block for latching a READ.sub.-- DATA from the LRU storing block to produce a DETECTED DATA and modifying it in response to the MODIFY CONTROL signal so as to produce a WRITE.sub.-- DATA to the LRU storing block; and a write way decoding block for analyzing the DETECTED DATA so as to produce a WRITE.sub.-- WAY. This LRU memory reduces the load of superscalar microprocessor required for controlling the cache memory, TLB and BTB and simplifies an interface therebetween, so as to perform the LRU updating process in high speed, thereby improving the performance of the superscalar microprocessor.