Processor bridge with dissimilar data registers which is operable to

Abstract

A bridge for a multi-processor system includes bus interfaces for connection to an I/O bus of a first processing set, an I/O bus of a second processing set and a device bus. A bridge control mechanism is configured to compare address and data phases of I/O accesses by the first and second processing sets. At least one dissimilar data register is provided for each processing set. The bridge control mechanism is operable in response to an address phase of a dissimilar data register write access to disregard any differences in the data phase for the dissimilar data write access. Non-deterministic data (for example relating to a real time clock) can be output from the processing sets in a combined (lockstep comparison) mode. A read destination address supplied in common by the first and second processing sets for a dissimilar data read access can cause data read from a determined one of the dissimilar data registers to be supplied the first and second processing sets. In this manner, the processing sets may have the dissimilar data replaced by the same data. The read destination address supplied in common by the first and second processing sets can determine the dissimilar data register from which data is read.