The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 24, 2000
Filed:
Nov. 24, 1998
Byeng-Sun Choi, Kyunggi-do, KR;
Young-Ho Lim, Kyungki-do, KR;
Abstract
A plurality of memory cell referenced regulators is connected to an output terminal that is configured to connect to a plurality of memory cells of a multi-level memory device. A respective one of the memory cell referenced regulators includes a respective dummy memory cell having a respective predetermined threshold voltage. The plurality of memory cell referenced regulators are responsive to a select signal such that a selected one of the memory cell referenced regulators varies a current at the output terminal to maintain the output terminal at a voltage proportional to the threshold voltage of the dummy memory cell of the selected memory cell referenced regulator. Each of the memory cell referenced regulators may comprise a variable current mirror having a controlled current path and an output current path including the output terminal. The controlled current path includes a controlled impedance therein that provides a variable impedance responsive to a control voltage applied thereto such that current produced at the output terminal is proportional to current in the controlled current path. A control voltage generator is connected between the output terminal and the controlled impedance and includes a dummy memory cell having a predetermined threshold voltage. The control voltage generator is operative to apply a control voltage to the controlled impedance to vary a current at the output terminal when an output voltage at the output terminal is greater than a predetermined voltage proportional to the predetermined threshold voltage of the dummy memory cell.