Low-power column parallel adc in cmos image sensors

Abstract

A low-power column parallel ADC architecture for image sensors that reduces the power consumption by reducing the number of switchings of a comparator to digitize a row of pixel data. Two ramp reference signals are provided in accordance with the principles of this invention. A first ramp signal is provided to each comparator that is clocked with an associated first clock signal. In each column comparator, the first ramp signal is compared to the pixel data using clock1, wherein clock1 corresponds to N multiple of a second clock signal (clock2), with N>1. Only when the column comparator detects a first crossover with the first ramp signal, then the comparator switches at every clock cycle of the second clock, clock2, to compare and detect a second crossover point with the second reference signal. This arrangement can greatly reduce the number of switchings required to digitize a row of pixel data, thereby resulting in significant power saving.