The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 24, 2000

Filed:

May. 25, 1999
Applicant:
Inventors:

Mitsuo Baba, Tokyo, JP;

Hiroki Teramoto, Tokyo, JP;

Assignee:

NEC Corporation, Tokyo, JP;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F / ;
U.S. Cl.
CPC ...
327295 ; 327141 ; 327156 ; 327158 ;
Abstract

A multiphase clock generating circuit having: a clock generating section for generating N-phase clock signals of number N which have a frequency nearly equal to that of input clock signal and whose phases are sequentially shifted by 360 degrees/N; an input side M-division circuit that divides the frequency of the input clock signal by M, outputting a reset signal to the clock generating section; an output side M-division circuit that is fed with a delayed reset signal that the reset signal output from the clock generating section is accompanied with a predetermined delay, and, synchronized with the delayed reset signal, divides the frequency of output clock signal output from the clock generating section by M; and a controller for comparing the input side M-division clock and the output side M-division clock, and controlling a delay amount of the clock generating section based on the comparison result.


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