Clock signal generator and data signal generator

Abstract

A comparator compares phases of an input data supplied from an input terminal and a synchronizing clock signal output by a variable counter, and outputting a comparison result signal indicative of any of a 'lead', a 'lag' and a 'non-detection' of the edge of the input data with respect to the up edge of the synchronizing clock signal. A state detector circuit detects the numbers of 'leads' and 'lags' in comparison result signals output by the comparator, and outputting a state detected signal indicative of any of 'the number of leads is larger', 'the number of lags is larger' and 'the number of leads is equal to the number of lags'. A dividing ratio selection circuit outputs a dividing ratio signal indicative of any of a 'dividing ratio smaller than a reference dividing ratio', a 'dividing ratio greater than the reference dividing ratio' and the 'reference dividing ratio', based on the comparison result signals output by the comparator and state detected signals output by the state detector circuit. A variable counter divides the frequency of a reference clock signal in response to the dividing ratio signal output by the dividing ratio selection circuit and outputs the result of the division to the comparator and an output terminal.