The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 24, 2000
Filed:
Jun. 24, 1999
Andreas Gehrmann, Dortmund, DE;
Erhard Muesch, Werne, DE;
Elmos Semiconductor AG, Dortmund, DE;
Abstract
The NMOS transistor is provided with a semiconducting substrate (12) which is p-doped and comprises a top side (14), and with a first region (16) which is n-doped and placed into the substrate by diffusion from the top side (14) of the substrate (12). Further, the transistor comprises a second region (18) arranged within the n-conducting region (16), which is n-doped and introduced into the substrate from the top side (14) of the substrate (12), and a field oxide layer (20) which is arranged on the top side (14) of the substrate (12) and limits the p-conducting region (16) on all sides. The top side comprises a source region (22) and a drain region (24) which are n-doped and arranged within the p-conducting region (18) at a distance to each other. A gate oxide layer (26) is arranged on the top side (14) of the substrate (12) between the source and the drain regions (22, 24). According to the invention it is envisaged that the p-conducting region (18) is placed into the n-conducting region (16) by means of ion implantation and that within the p-conducting region (18) the ion concentration on the top side (14) of the substrate (12) is smaller than that at the lower limit, located within the substrate (12), between the n-conducting region (16) and the p-conducting region (18).