The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 17, 2000

Filed:

Aug. 15, 1996
Applicant:
Inventors:

Anthony John Holmes, Nr. Reading, GB;

Mark Elliott, Berkshire, GB;

Ian Nicholas Cottam, Basingstoke, GB;

John Harper, Golfe Juan, FR;

Martin Stratford, Herefordshire, GB;

Assignee:

Digital Esquipment Corporation, Houston, TX (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F / ;
U.S. Cl.
CPC ...
711213 ; 711137 ; 711204 ; 710 22 ; 710129 ;
Abstract

A digital system has a main memory 10 with a main memory access (DMA) unit 11 through which data channels 12, 13 are coupled to the memory. A processor system (processor 14, RAM data memory 15, instruction memory 16) is also coupled to the memory through a read/write buffer 20, each read stalling the processor for typically 5 cycles. For block reads, a block memory read unit 25 is connected in parallel with the path between the read/write buffer 20 and the DMA unit 11. This block read unit can be set from the processor 14 with a block start address and a block length passed as writes through the read/write buffer 20. The block is read (first phase) word by word from the main memory via the DMA unit into a memory 28 in the block read unit. The processor then sends a command to the block read unit as a read through the read/write buffer, which then writes the block word by word directly into the memory 15 (second phase), using the processor's local data and address buses 17 and 18 and disabling the processor's address buffer 32.


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