The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 17, 2000
Filed:
Mar. 06, 1998
Luigi Ternullo, Jr, San Jose, CA (US);
Vanguard International Semiconductor Corp, Hsinchu, TW;
Abstract
A crow-bar current reduction circuit for use with a NMOS output circuit a gate voltage control circuit (GVC). The GVC receives a data signal and an output enable signal and generates control signals to drive the gates of the output transistors of the output circuit. When enabled, the GVC delays the rising edges of the gate control signals so as to help ensure that during a transition of the output signal generated by the output circuit, the NFET that was conductive before the transition is 'turned off' to become non-conductive before the NFET that was non-conductive before the transition is 'turned on' to become conductive. When adapted for a CMOS output circuit, the GVC delays the rising edge of the gate control signal provided to the NMOS pull-down transistor and delays the falling edge of gate control signal provided to the PMOS pull-up transistor.