The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 17, 2000

Filed:

Aug. 25, 1998
Applicant:
Inventors:

Shi-Woo Rhee, Pohang-shi, KR;

Jong-Ho Yun, Pohang-shi, KR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L / ; B05D / ;
U.S. Cl.
CPC ...
438677 ; 438672 ; 438675 ; 427 97 ; 427 99 ; 427282 ;
Abstract

A process for preparing a metallic interconnecting plug in a semiconductor device which comprises the steps of: i) forming an insulating layer on the surface of a semiconductor substrate or a metal underlayer of the semiconductor device, ii) forming a hole in the insulating layer to expose the surface of the semiconductor substrate or the metal underlayer, iii) exposing the surface of the insulating layer to the vapor of a blocking agent under a pressure ranging from 10.sup.-12 to 10 torr for a controlled time period so that a blocking layer is formed only on the outer surface of the insulating layer, the blocking layer not extending over the inside walls of the hole, iv) selectively depositing a conductive metal in the hole using a chemical vapor deposition method to form the metallic interconnecting plug which extends from the surface of the semiconductor substrate or the metal underlayer to the level of the outer surface of the insulating layer, and v) removing the blocking layer from the surface of the insulating layer.


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