The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 10, 2000
Filed:
May. 02, 1997
Michael Patrick Beakes, Yorktown Heights, NY (US);
Barbara Alana Chappell, Portland, OR (US);
Terry Ivan Chappell, Portland, OR (US);
Gary S Ditlow, Garrison, NY (US);
Barry Lee Dorfman, Austin, TX (US);
Bruce Martin Fleischer, Mount Kisco, NY (US);
Vinod Narayanan, Fishkill, NY (US);
Robert Alan Philhower, Carmel, NY (US);
George Anthony Halasz, Mount Kisco, NY (US);
Ghavam Ghavami Shahidi, Emsford, NY (US);
David James Widiger, Pflugerville, TX (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
A computer-based method automatically synthesizes, optimizes and compiles high performance control logic using SRCMOS LOGIC ARRAY MACROS, abbreviated as SLAMs. The method includes a series of steps that transform a high level design description into a set of SLAMs, and includes the steps of partitioning the logic description of a unit into blocks that are suitable for mapping to a target SLAM structure; mapping each logic partition to the target SLAM structure; creating a configuration and relative layout for the internal structure for each SLAM; creating an external description for each SLAM, each description being of sufficient detail to carry out physical design and integration of the unit which contains the SLAM; assembling the partitions implemented as SLAMs with other macros in the unit; resolving interface conflicts between the different macros by selecting appropriate signal interfaces for various SLAMs; repeatedly changing the external specifications of the various SLAMs; analyzing the performance of the unit; automatically compiling the schematic and layout of each SLAM within the unit based on the configuration and relative layout; and assembling the macros and analyzing the design for design rule violations.