Semiconductor ic device having a control register for designating memory

Abstract

A semiconductor integrated circuit device having a processing unit and a memory which stores data to be processed by the processing unit and which provides data to the processing unit through the data bus in response to accessing instructions from the processing unit through the address bus. The memory has a plurality of memory blocks each of which has a plurality of electrically programmable nonvolatile memory cells arranged in rows and columns in which each nonvolatile memory cell is coupled to one of a plurality of word lines and one of a plurality of data lines of the memory. The memory blocks formed can be facilitated with different memory capacities, including through controlling the number of rows or columns of memory cells associated therewith. Sources of all of the memory cells within each memory block are connected to a single source line which is fed by a predetermined voltage from a corresponding one of plural source voltage control circuits, for flash erasing the memory cells in that memory block in an erasing operation. The device also features a control register which, under the control of the processing unit, designates one or more of the memory blocks to be simultaneously erased.