The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 03, 2000
Filed:
Jun. 11, 1998
Chiakang Sung, Milpitas, CA (US);
Wanli Chang, Saratoga, CA (US);
Joseph Huang, San Jose, CA (US);
Richard G Cliff, Los Altos, CA (US);
L Todd Cope, San Jose, CA (US);
William Leong, deceased, late of R.C., CA (US);
by Louis Leong, legal representative, San Leandro, CA (US);
Altera Corporation, San Jose, CA (US);
Abstract
A programmable logic array integrated circuit device has a relatively large block of programmable memory cells in addition to the usual programmable logic modules and the usual programmable interconnection conductor network. In order to simplify the circuitry associated with the large block, and especially the circuitry for addressing that block during programming and/or verification of the device, the address decoder that is normally used to address the block during use of the device to perform logic is also used during programming and/or verification. During programming and/or verification a counter or other similar coded address signal generating circuitry is used to supply address information to the decoder.