The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 03, 2000

Filed:

Nov. 01, 1999
Applicant:
Inventor:

Kenichi Serizawa, Kanagawa, JP;

Assignee:

NEC Corporation, Tokyo, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C / ; G11C / ;
U.S. Cl.
CPC ...
365154 ; 365156 ; 365190 ;
Abstract

A semiconductor memory device in an SRAM using a 4 transistor-type memory cell which device includes an error writing protection circuit for preventing any information from being written into a memory cell into which any information is not needed to be written owing to line capacitance between adjacent bit lines. The error writing protection circuit includes an N-type transistors, a P-type transistor, and diodes. Hereby, it is determined whether or not a bit line is charged with electricity in accordance with electric potential of an adjacent bit line, and there is not charged with electricity a bit line for which there is no possibility of any information from being written, but there is charged with electricity only bit lines where there is possibility of any information being written in error. Thus, there is flowed no excess current.


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Serizawa, Kenichi. (2000). Semiconductor memory device (U.S. Patent No. 6128217). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/6128217

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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