The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 03, 2000
Filed:
Mar. 13, 1998
Ichiro Kumata, Kanagawa, JP;
Sony Corporation, Tokyo, JP;
Abstract
A delay circuit is constituted by connecting a plurality of delay elements in series, each delay element is constituted by a pMOS transistor P1 and a nMOS transistor N1 having a larger driving capability than P1 and by a nMOS transistor N2 and a pMOS transistor P2 having a larger driving capability than N2, an input signal is applied to the gate of the transistor P1, a precharge signal is applied to the gate of the transistor N1, an inverted signal of the precharge signal is applied to the gate of the transistor P2, the gate of the transistor N2 is connected to an intermediate node A, an input signal S.sub.IN is input to each delay element as the precharge signal, and when the input signal S.sub.IN is at a high level, the node A is in the state of a low level and the output terminal OUT is in the state of a high level, the falling edge of the input signal S.sub.IN is sequentially propagated by delay elements, and thus a delay signal is obtained.