Temporally redundant latch for preventing single event disruptions in

Abstract

A temporally redundant latch for use in integrated circuit (IC) devices redundantly samples data output from logic or other circuitry at multiple time-shifted periods to provide multiple, independent data samples from which a correct data sample can be selected. The latch has three sampling circuits (e.g., D flip-flops or DICE latches) that sample the logic data output at three different and distinct sampling times. The latch also has a sample release circuit coupled to the sampling circuits to select and output a majority of the samples collected by the sampling circuits at a fourth time that again is different and distinct from the three sampling times. The latch affords both spatial parallelism due to the multiple parallel sampling circuits and temporal parallelism resulting from the clocking scheme involving multiple time-spaced clock signals. The temporally redundant latch is immune to upsets that might occur in the latch itself, as well as upsets that occur in the circuitry and upsets that might occur in any clocking and control signals on the IC device.