The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 03, 2000

Filed:

Feb. 03, 2000
Applicant:
Inventor:

Takuya Ishida, Kyoto, JP;

Assignee:

Rohm Co., Ltd., Kyoto, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11B / ;
U.S. Cl.
CPC ...
318565 ; 318490 ; 369 53 ;
Abstract

In a semiconductor integrated circuit device, after electric power starts being supplied thereto, when a control circuit 2 is turned on, a test signal is fed in via a clock output terminal 6. At this time, an on/off control signal is at a low level, which causes a controller 14 to feed a low-level signal through a buffer 17 to the gate terminal G of a latch circuit 15, and thus the test signal fed through a buffer 9 to the input terminal D of the latch circuit 15 is fed from the output terminal Q thereof to the controller 14. Having received the test signal, the controller 14 recognizes establishment of a test mode and turns the on/off control signal to a high level. This causes the latch circuit 15 to stop operating, and thus the controller 14 feeds a clock through an AND circuit 16 and a buffer 8 to a clock output terminal 6 for external output.


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