The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 03, 2000
Filed:
Jun. 24, 1998
Applicant:
Inventors:
Zoran Krivokapic, Santa Clara, CA (US);
Ognjen Milic, Burlingame, CA (US);
Assignee:
Advanced Micro Devices, Sunnyvale, CA (US);
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L / ; H01L / ;
U.S. Cl.
CPC ...
257505 ; 257506 ; 257508 ; 257618 ; 257623 ;
Abstract
A totally self-aligned transistor with shallow trench isolation. A single mask is used to align the source, drain, gate and isolation areas. Overlay error is greatly reduced by the use of a single mask for these regions. Channel dopant deposited in the gate area is also self-aligned to the gate of the transistor.
Quick Actions:
Krivokapic, Zoran. (2000). Totally self-aligned transistor with polysilicon shallow trench isolation (U.S. Patent No. 6127717). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/6127717
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile