The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 03, 2000
Filed:
May. 05, 1999
Chang-Feng Wan, Dallas, TX (US);
Richard Scott List, Dallas, TX (US);
Curtis Gene Garrett, Garland, TX (US);
Dwight U Bartholomew, Dallas, TX (US);
DRS Technologies, Inc., Parsippany, NJ (US);
Abstract
This invention relates to mounting integrated circuits (IC) to multi-chip modules (MCM) or substrates. More specifically, it provides a method of mounting a semiconductor die such as a thin slice of Mercury Cadmium Telluride (MCT) to a silicon semiconductor substrate, a read-out integrated circuit (ROIC), using a thermoplastic to reduce stress on the MCT caused by mismatched Coefficients of Thermal Expansion (CTE). This process provides for an array of infrared photodetectors on a material such as MCT to be mounted to a read-out integrated circuit (ROIC) using the Vertical Integrated Photodiode (VIP) approach to FPAs, while allowing double sided interdiffusion of CdTe for surface passivation to reduce dark currents and improve performance, without the problems associated with mismatched coefficients of thermal expansion during high temperature processes.