The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 03, 2000
Filed:
Mar. 13, 1998
Robert D Tolles, Santa Clara, CA (US);
Norm Shendon, San Carlos, CA (US);
Sasson Somekh, Los Altos Hills, CA (US);
Ilya Perlov, Santa Clara, CA (US);
Eugene Gantvarg, Santa Clara, CA (US);
Harry Q Lee, Mountain View, CA (US);
Applied Materials, Inc., Santa Clara, CA (US);
Abstract
An apparatus and associated methods for polishing semiconductor wafers and other workpieces that includes a polishing surfaces, such as pads mounted on respective platens, located at multiple polishing stations. Multiple wafer heads, preferably at least one greater in number than the number of polishing stations, can be loaded with individual wafers. The wafer heads are suspended from a rotatable support, which provides circumferential positioning of the heads relative to the polishing surfaces, and the wafer heads move linearly with respect to the polishing surface, for example oscillate radially within the rotatable support. A load/unload station may be located at a position symmetric with the polishing surfaces. The rotatable support can simultaneously position one of the heads over the load/unload station while the remaining heads are located over polishing stations for wafer polishing so that loading and unloading of wafers can be performed concurrently with wafer polishing. The multiple polishing stations can be used to sequentially polish a wafer held in a wafer head in a step of multiple steps. The steps may be equivalent, may provide polishes of different finish, or may be directed to polishing different levels. Alternately, more than one wafer may equivalently be polished at multiple polishing stations.