Storing executing instruction sequence for re-execution upon backward

Abstract

A controller for a digital processor includes a random access memory, e.g., an instruction memory, that consumes significant power when operating. To reduce the power consumption when repetitive instructions, i.e. loops, are being performed, the instructions being executed are stored in a shift register and, when a jump-back instruction is executed, the instructions, including those in the loop, are then accessed from the shift register rather than from the random access memory without any additional special instructions that define the characteristics of the loop. A memory control includes a state tracking machine that monitors the execution of the program instructions and determines from the execution of a jump-back instruction that a loop may have been entered, whereupon it enables the shift register to produce the instructions stored therein and disables the instruction memory from producing instructions that are stored in the shift register. The foregoing process preferably is automatically initiated for each loop, whether the loop is a new loop, a loop within a loop or a multiple loop.