The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 26, 2000
Filed:
Mar. 05, 1998
Joel D Buck-Gengler, Longmont, CO (US);
Hewlett-Packard Company, Palo Alto, CA (US);
Abstract
A virtual linear frame buffer addressing method and apparatus efficiently convert a linear address supplied by an application programming (API) into an X, Y address used in a rectangular memory addressing arrangement. The virtual linear frame buffer addressing logic allows rectangular memory addressing to coexist in an environment that requires the use of linear memory addressing by creating a table of address ranges, byte stride values and physical address offset descriptors. The address ranges and byte stride values are associated with particular sections of frame buffer memory. An offset descriptor is associated with each section of physical memory. The address ranges, byte stride values and offset descriptors are placed into a table. When a linear address is received from an API, the address range is determined. The lower bound of the address range is the base address. The base address is subtracted from the linear address resulting in a local linear address. Based upon the address range, a particular byte stride value is selected from the table and used to divide the local address resulting in an X, Y location corresponding to the linear address. The X, Y location and the offset descriptor are supplied to a memory controller, such as a graphics memory controller, which then determines the physical address corresponding to the linear address.