High-speed push-pull output stage for logic circuits

Abstract

A logic circuit output stage includes a first transistor with a first terminal that receives the first logic output signal and a third terminal coupled to a first output node. A second transistor has a first terminal coupled to the first terminal of the first transistor. A third transistor has a first terminal that receives the second logic output signal and a third terminal coupled to a second output node. A fourth transistor has a first terminal coupled to a third terminal of the second transistor and a second terminal coupled to the second output node. An impedance is connected between the third terminal of the second transistor and the first output node. In this output stage, the second transistor provides a transient signal to the first terminal of the fourth transistor in response to a transition in the first logic output signal. The fourth transistor provides a temporary change in the current flowing through the second output node in response to the transient signal received from the second transistor. The temporary current change provided by the fourth transistor allows faster charging or discharging of capacitive loads on the second output node, thereby producing a faster output slew rate. Moreover, the faster output slew rate is produced without significantly increasing either the integrate circuit chip area or the power consumed by the output stage.