The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 26, 2000
Filed:
Jun. 17, 1999
Applicant:
Inventors:
Mark S Rodder, University Park, TX (US);
William U Liu, Plano, TX (US);
Assignee:
Texas Instruments Incorporated, Dallas, TX (US);
Primary Examiner:
Int. Cl.
CPC ...
H01L / ;
U.S. Cl.
CPC ...
257616 ; 257751 ; 438300 ;
Abstract
A MOSFET (100) having a heterostructure raised source/drain region and method of making the same. A two layer raised source drain region (106) is located adjacent a gate structure (112). The first layer (106a) is a barrier layer comprising a first material (e.g., SiGe, SiC). The second layer (106b) comprises a second, different material (e.g. Si). The material of the barrier layer (106a) is chosen to provide an energy band barrier between the raised source/drain region (106) and the channel region (108).