The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 26, 2000
Filed:
Aug. 26, 1999
Kuan-Chou Sung, Taoyuan, TW;
Chien Chou, Chiayi Hsien, TW;
Steve Hsu, Hsinchu Hsien, TW;
Elmer Chen, Taipei, TW;
Mosel Vitelic, Inc., Hsinchu, TW;
Abstract
A method for forming a MOSFET device on a semiconductor substrate is disclosed here. First, a gate oxide layer, a polysilicon layer, a metal silicide layer and a silicon oxynitride layer are formed on the semiconductor substrate in sequence. Then, the silicon oxynitride layer, the metal silicide layer, the polysilicon layer and the gate oxide layer are etched to define a gate pattern. The sidewall spacers are formed on the sidewalls of the gate structure. The source and drain areas are defined by forming the doping areas in the semiconductor substrate. Next, a non-doped dielectric layer is formed above the semiconductor substrate to cover the gate structure, the sidewall spacers and the source/drain areas. An annealing procedure is next performed about 10 to 15 minutes at a temperature of about 800 to 850.degree. C. Then, a dielectric layer is formed on said non-doped dielectric layer.
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile