The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 19, 2000

Filed:

Sep. 05, 1997
Applicant:
Inventors:

Douglas N Krening, Larkspur, CO (US);

Gregory B Lannan, Larkspur, CO (US);

Michael J Schneiderwind, Castle Rock, CO (US);

Robert A Schneiderwind, Castle Rock, CO (US);

Robert T Caffrey, Silver Spring, MD (US);

Assignee:

First Pass Inc., Castle Rock, CO (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F / ;
U.S. Cl.
CPC ...
713323 ; 712 20 ; 712 32 ; 712 10 ; 712 11 ; 712 13 ; 712 15 ; 326 39 ; 326 41 ; 710101 ;
Abstract

A single chip application specific integrated circuit (ASIC) which provides a flexible, modular interface between a subsystem and a standard system bus. The ASIC includes a microcontroller/microprocessor, a serial interface for connection to the bus, and a variety of communications interface devices available for coupling to the subsystem. A three-bus architecture, utilizing arbitration, provides connectivity within the ASIC and between the ASIC and the subsystem. The communication interface devices include UART (serial), parallel, analog, and external device interface utilizing bus connections paired with device select signals. A low power (sleep) mode is provided as is a processor disable option.


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