Pci bus utilization diagnostic monitor

Abstract

The present invention provides a PCI Bus Diagnostic Monitor which eliminates the need to hook up a logic analyzer and manually analyze the data passing on the PCI Bus. The present invention provides an accurate analysis of the PCI Bus master's utilization and/or latency time to acquire the PCI Bus by controlling a 12-bit counter and analyzing count values at appropriate times, e.g., between the time the PCI Bus request is output and the time that the data transfer begins, and the time between when the data transfer begins and when the data transfer ends. The data corresponding to a large number of data transfers may be buffered and analyzed to provide performance statistics relating to the PCI Bus. The analysis can be performed in lightly loaded, typically loaded, and heavily loaded PCI bus situations to fully and accurately test real-world capabilities of new peripherals, particular combinations of peripherals, and statistics relating to customized usage of a host system. The accurate statistics relating to the performance of the PCI Bus will also allow a system designer to assign and/or reassign PCI Bus priorities for various bus agents or peripherals.