Master dma controller with re-map engine for only spawning programming

Abstract

A computer system implementing a distributed direct memory access architecture is disclosed. The computer system includes a re-map engine that includes control logic and a shadow register for each distributed DMA channel. Each shadow register includes 16 bytes of DMA configuration information that mirrors the current programming of the associated distributed DMA channel. When the CPU needs to program one or more DMA channels, the CPU sends a DMA master programming cycle to the control logic in the re-map engine. The re-map control logic compares the configuration data in the master cycle with the contents of the shadow registers and spawns daughter programming cycles to just those distributed channels for which a mismatch condition exists. If a match exists with respect to a particular channel, indicating that the new programming data is no different than the current programming of the channel, the control logic does not spawn a daughter programming cycle to that channel. If the control logic determines that a mismatch condition exists, the control logic updates the contents of the effected shadow register while spawning the daughter cycle to the distributed channel to be reprogrammed. By spawning only those daughter programming cycles necessary to actually reprogram the DMA system, the distributed DMA system of the present invention requires less bus traffic and thus is more efficient.